Embodiments of the present invention relate to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device including a buried gate and a method for forming the same.
Recently, most electronic appliances comprise a semiconductor device. Semiconductor devices comprise electronic elements such as transistors, resistors and capacitors. These electronic elements are designed to perform electronic functions and are integrated on a semiconductor substrate. For example, an electronic appliance, such as a computer or a digital camera, includes a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
Semiconductor devices must increase in integration degree in order to satisfy consumer demands for superior performance and low prices. Such an increase in the integration degree of a semiconductor device entails a reduction in a design rule, causing patterns of a semiconductor device to be increasingly reduced. Although an entire chip area increases in proportion to an increase in memory capacity as a semiconductor device becomes super miniaturized and highly integrated, a cell area, where patterns of a semiconductor device are actually formed, decreases. Accordingly, since a greater number of patterns should be formed in a limited cell area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced minimum pattern size.
A dynamic random access memory (DRAM) device includes a plurality of unit cells each having a capacitor and a transistor. The capacitor is used to temporarily store data, and the transistor is used to transfer data between a bit line and the capacitor in response to a control signal (word line). Data transfer occurs by using the semiconductor property that electrical conductivity changes depending on the environment. A transistor has three regions, i.e., a gate, a source, and a drain. Electric charges move between the source and the drain according to a control signal input to the gate of the transistor. The movement of the electric charges between the source and the drain is achieved through a channel region, where the semiconductor property is utilized.
In a conventional method for manufacturing a transistor, a gate is formed in a semiconductor substrate, and a source and a drain are formed by doping impurities into both sides of the gate. A channel region of the transistor is formed between the source and the drain under the gate. The transistor has a horizontal channel region and occupies a predetermined area of a semiconductor substrate. Therefore, for a given transistor, the number of memory cells may determine the size of the semiconductor device.
If the total area of the semiconductor memory device is reduced, the number of semiconductor memory devices per wafer increases, thereby improving productivity. Several methods for reducing the total area of a semiconductor memory device have been proposed. One method is to replace a conventional planar gate, having a horizontal channel region, with a recess gate in which a recess is formed in a substrate and a channel region is formed along a curved surface of the recess by forming a gate in the recess. In addition, a buried gate has been studied, which can reduce parasitic capacitance of a bit line by burying the entire gate within a recess.
In a semiconductor device that has a buried gate, a bit line contact plug is coupled to an active region of the semiconductor substrate including the buried gate. A conventional method for forming a bit line contact plug will hereinafter be described in detail.
An interlayer insulation film is formed over a semiconductor substrate, including a buried gate, and the interlayer insulation film is etched to expose an active region so that a bit line contact hole is formed. A lower part of the bit line contact hole is formed to sufficiently cover the active region. Subsequently, a spacer is formed at sidewalls of a bit line contact hole, and a bit line contact plug is formed to bury the bit line contact hole. An upper part of the bit line contact plug is formed to be larger than the lower part thereof by the spacer, so that tolerance for forming a storage node contact plug in a subsequent process is reduced. As a result, the storage node contact plug is not open and thus the storage node contact plug fails to be coupled to the active region, resulting in deterioration of semiconductor device characteristics.